// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.198 on Mon Sep 22 23:45:53 2025
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[11], immediateIndexed
dcl_constantbuffer CB1[137], immediateIndexed
dcl_constantbuffer CB2[682], dynamicIndexed
dcl_resource_structured t0, 16
dcl_resource_structured t1, 16
dcl_uav_structured u0, 4
dcl_uav_structured u1, 4
dcl_uav_structured u2, 4
dcl_input vThreadID.xyz
dcl_temps 31
dcl_thread_group 4, 4, 4
dcl_constantbuffer CB14[2], immediateIndexed
ult [precise(xyz)] r0.xyz, vThreadID.xyzx, cb0[8].xyzx
and [precise(x)] r0.x, r0.y, r0.x
and [precise(x)] r0.x, r0.z, r0.x
if_nz r0.x
  imad r0.x, vThreadID.z, cb0[8].y, vThreadID.y
  imad r0.x, r0.x, cb0[8].x, vThreadID.x
  ishl r1.x, l(1), cb0[10].z
  utof r1.x, r1.x
  mul r1.xy, r1.xxxx, cb1[136].zwzz
  mul r1.xy, r1.xyxx, l(2.000000, -2.000000, 0.000000, 0.000000)
  utof r2.xyz, vThreadID.xyzx
  mad r1.zw, r2.xxxy, r1.xxxy, l(0.000000, 0.000000, -1.000000, 1.000000)
  iadd r2.xyw, vThreadID.xyxz, l(1, 1, 0, 1)
  utof r3.xyz, r2.xywx
  mad r1.xy, r3.xyxx, r1.xyxx, l(-1.000000, 1.000000, 0.000000, 0.000000)
  div r2.x, r2.z, cb0[9].z
  exp r2.x, r2.x
  add r2.x, r2.x, -cb0[9].y
  div r2.x, r2.x, cb0[9].x
  ieq r2.y, vThreadID.z, cb0[8].z
  movc r2.x, r2.y, l(2000000.000000), r2.x
  movc r2.z, vThreadID.z, r2.x, l(0)
  div r3.x, r3.z, cb0[9].z
  exp r3.x, r3.x
  add r3.x, r3.x, -cb0[9].y
  div r3.x, r3.x, cb0[9].x
  ieq r2.w, r2.w, cb0[8].z
  movc r3.z, r2.w, l(2000000.000000), r3.x
  ge r2.w, cb1[31].w, l(1.000000)
  mad r3.w, r2.z, cb1[30].z, cb1[31].z
  add r4.x, r2.z, cb1[66].w
  mul r4.x, r4.x, cb1[66].z
  div r4.x, l(1.000000, 1.000000, 1.000000, 1.000000), r4.x
  movc r3.w, r2.w, r3.w, r4.x
  mul r26.x, cb14[0].y, r3.w
  add r26.y, l(1.000000), r26.x
  mul r26.y, r26.y, l(2.000000)
  mad r1.z, cb14[0].x, -r26.y, r1.z
  mad r1.x, cb14[0].x, r26.y, r1.x
  mul r4.xyz, r1.wwww, cb1[37].xywx
  mad r5.xyz, r1.zzzz, cb1[36].xywx, r4.xyzx
  mad r6.xyz, r3.wwww, cb1[38].xywx, r5.xyzx
  add r6.xyz, r6.xyzx, cb1[39].xywx
  mul r7.xyz, r1.yyyy, cb1[37].xywx
  mad r8.xyz, r1.xxxx, cb1[36].xywx, r7.xyzx
  mad r9.xyz, r3.wwww, cb1[38].xywx, r8.xyzx
  add r9.xyz, r9.xyzx, cb1[39].xywx
  mad r1.yzw, r1.zzzz, cb1[36].xxyw, r7.xxyz
  mad r7.xyz, r3.wwww, cb1[38].xywx, r1.yzwy
  add r7.xyz, r7.xyzx, cb1[39].xywx
  mad r4.xyz, r1.xxxx, cb1[36].xywx, r4.xyzx
  mad r10.xyz, r3.wwww, cb1[38].xywx, r4.xyzx
  add r10.xyz, r10.xyzx, cb1[39].xywx
  mad r1.x, r3.z, cb1[30].z, cb1[31].z
  add r3.w, r3.z, cb1[66].w
  mul r3.w, r3.w, cb1[66].z
  div r3.w, l(1.000000, 1.000000, 1.000000, 1.000000), r3.w
  movc r1.x, r2.w, r1.x, r3.w
  mad r5.xyz, r1.xxxx, cb1[38].xywx, r5.xyzx
  add r5.xyz, r5.xyzx, cb1[39].xywx
  mad r8.xyz, r1.xxxx, cb1[38].xywx, r8.xyzx
  add r8.xyz, r8.xyzx, cb1[39].xywx
  mad r1.yzw, r1.xxxx, cb1[38].xxyw, r1.yyzw
  add r1.yzw, r1.yyzw, cb1[39].xxyw
  mad r4.xyz, r1.xxxx, cb1[38].xywx, r4.xyzx
  add r4.xyz, r4.xyzx, cb1[39].xywx
  div r6.xy, r6.xyxx, r6.zzzz
  div r6.zw, r9.xxxy, r9.zzzz
  div r7.xy, r7.xyxx, r7.zzzz
  div r7.zw, r10.xxxy, r10.zzzz
  div r5.xy, r5.xyxx, r5.zzzz
  div r5.zw, r8.xxxy, r8.zzzz
  div r1.xy, r1.yzyy, r1.wwww
  div r1.zw, r4.xxxy, r4.zzzz
  min r4.xy, r6.zwzz, r6.xyxx
  min r4.xy, r7.xyxx, r4.xyxx
  min r4.xy, r7.zwzz, r4.xyxx
  min r4.xy, r5.xyxx, r4.xyxx
  min r4.xy, r5.zwzz, r4.xyxx
  min r4.xy, r1.xyxx, r4.xyxx
  min r2.xy, r1.zwzz, r4.xyxx
  max r4.xy, r6.zwzz, r6.xyxx
  max r4.xy, r7.xyxx, r4.xyxx
  max r4.xy, r7.zwzz, r4.xyxx
  max r4.xy, r5.xyxx, r4.xyxx
  max r4.xy, r5.zwzz, r4.xyxx
  max r1.xy, r1.xyxx, r4.xyxx
  max r3.xy, r1.zwzz, r1.xyxx
  add r1.xyz, r2.xyzx, r3.xyzx
  mad r2.xyz, -r1.xyzx, l(0.500000, 0.500000, 0.500000, 0.000000), r3.xyzx
  imul null, r1.w, cb0[10].y, cb0[10].x
  ishl r1.w, r1.w, l(1)
  mov r0.yw, l(0,0,0,0)
  mov r2.w, l(0)
  loop
    uge r3.x, r2.w, cb0[9].w
    breakc_nz r3.x
    ld_structured_indexable(structured_buffer, stride=16)(mixed,mixed,mixed,mixed) r3.xyzw, r2.w, l(0), t0.xyzw
    mad r4.xyz, -r1.xyzx, l(0.500000, 0.500000, 0.500000, 0.000000), r3.xyzx
    add r4.xyz, -r2.xyzx, |r4.xyzx|
    max r4.xyz, r4.xyzx, l(0.000000, 0.000000, 0.000000, 0.000000)
    dp3 r4.x, r4.xyzx, r4.xyzx
    mul r3.w, r3.w, r3.w
    lt r3.w, r4.x, r3.w
    if_nz r3.w
      ld_structured_indexable(structured_buffer, stride=16)(mixed,mixed,mixed,mixed) r4.xyzw, r2.w, l(0), t1.xyzw
      lt r3.w, l(0.000000), r4.w
      mad r3.xyz, r1.xyzx, l(0.500000, 0.500000, 0.500000, 0.000000), -r3.xyzx
      mul r5.xyz, -r4.xyzx, r3.yzxy
      mad r5.xyz, r3.xyzx, -r4.yzxy, -r5.xyzx
      mul r6.xyz, -r4.yzxy, r5.xyzx
      mad r5.xyz, r5.zxyz, -r4.zxyz, -r6.xyzx
      dp3 r5.w, r5.xyzx, r5.xyzx
      rsq r5.w, r5.w
      mul r5.xyz, r5.wwww, r5.xyzx
      mad r4.xyz, r4.wwww, r4.xyzx, -r5.xyzx
      dp3 r3.x, r3.xyzx, r4.xyzx
      dp3 r3.y, r2.xyzx, |r4.xyzx|
      ge r3.x, r3.y, r3.x
      movc r3.x, r3.w, r3.x, l(-1)
      if_nz r3.x
        imm_atomic_iadd r3.x, u0, l(0, 0, 0, 0), l(1)
        ult r3.y, r3.x, r1.w
        if_nz r3.y
          imm_atomic_exch r4.x, u1, r0.xyxx, r3.x
          ishl r3.y, r3.x, l(1)
          store_structured u2.x, r3.y, l(0), r2.w
          bfi r3.x, l(31), l(1), r3.x, l(1)
          store_structured u2.x, r3.x, l(0), r4.x
        endif
      endif
    endif
    iadd r2.w, r2.w, l(1)
  endloop
  iadd r0.z, r0.x, cb0[10].x
  mov [precise(x)] r0.x, l(0)
  loop
    uge [precise(y)] r0.y, r0.x, cb0[8].w
    breakc_nz r0.y
    add [precise(xyz)] r3.xyz, cb1[72].xyzx, cb2[r0.x + 0].xyzx
    add [precise(xyz)] r4.xyz, r3.xyzx, -cb2[r0.x + 0].xyzx
    add [precise(xyz)] r5.xyz, r3.xyzx, -r4.xyzx
    add [precise(xyz)] r5.xyz, -r5.xyzx, cb2[r0.x + 0].xyzx
    add [precise(xyz)] r4.xyz, -r4.xyzx, cb1[72].xyzx
    add [precise(xyz)] r4.xyz, r4.xyzx, r5.xyzx
    add r5.xyz, cb1[73].xyzx, cb2[r0.x + 341].xyzx
    add r4.xyz, r4.xyzx, r5.xyzx
    add r3.xyz, r3.xyzx, r4.xyzx
    mul r4.xyz, r3.yyyy, cb1[13].xyzx
    mad r3.xyw, r3.xxxx, cb1[12].xyxz, r4.xyxz
    mad r3.xyz, r3.zzzz, cb1[14].xyzx, r3.xywx
    add r3.xyz, r3.xyzx, cb1[15].xyzx
    mad r3.xyz, -r1.xyzx, l(0.500000, 0.500000, 0.500000, 0.000000), r3.xyzx
    add r3.xyz, -r2.xyzx, |r3.xyzx|
    max r3.xyz, r3.xyzx, l(0.000000, 0.000000, 0.000000, 0.000000)
    dp3 r0.y, r3.xyzx, r3.xyzx
    mul r2.w, cb2[r0.x + 0].w, cb2[r0.x + 0].w
    lt r0.y, r0.y, r2.w
    if_nz r0.y
      imm_atomic_iadd r3.x, u0, l(0, 0, 0, 0), l(1)
      ult r0.y, r3.x, r1.w
      if_nz r0.y
        imm_atomic_exch r4.x, u1, r0.zwzz, r3.x
        ishl r0.y, r3.x, l(1)
        store_structured u2.x, r0.y, l(0), r0.x
        bfi r2.w, l(31), l(1), r3.x, l(1)
        store_structured u2.x, r2.w, l(0), r4.x
      endif
    endif
    iadd [precise(x)] r0.x, r0.x, l(1)
  endloop
endif
ret
// Approximately 0 instruction slots used
