// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using SLT v0.6.750 on Sat May 23 19:19:35 2026
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_VertexID              0   x           0   VERTID    uint   x
// ATTRIBUTE                0   xyz         1     NONE   float   xyz
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// TEXCOORD                 0   xyzw        0     NONE   float   xyzw
// SV_POSITION              0   xyzw        1      POS   float   xyzw
// P                        0   x           2  RTINDEX    uint   x
//
vs_5_0
dcl_output_siv o2.x, rendertarget_array_index
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[10], immediateIndexed
dcl_constantbuffer CB1[4], immediateIndexed
dcl_input_sgv v0.x, vertex_id
dcl_input v1.xyz
dcl_output o0.xyzw
dcl_output_siv o1.xyzw, position
dcl_temps 40
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r38.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o2.x, r38.z
ld_indexable(buffer)(float,float,float,float) r25.xyzw, l(0, 0, 0, 0), t125.xyzw
ftou r0.x, cb0[5].x
if_nz r0.x
  utof r0.y, r0.x
  div r0.z, l(3.14159274), r0.y
  sincos null, r0.z, r0.z
  div r0.z, l(1.000000, 1.000000, 1.000000, 1.000000), r0.z
  sincos r1.x, r2.x, cb0[5].z
  mul r0.w, r2.x, cb0[5].w
  div r1.x, r1.x, r2.x
  ftou r1.y, cb0[5].y
  imul null, r1.z, r0.x, r1.y
  ult r1.w, v0.x, r1.z
  if_nz r1.w
    udiv r2.x, r3.x, v0.x, r0.x
    ishl r1.w, r3.x, l(1)
    utof r1.w, r1.w
    mul r1.w, r1.w, l(3.14159274)
    div r1.w, r1.w, r0.y
    utof r2.x, r2.x
    mul r2.x, r0.w, r2.x
    iadd r2.y, r1.y, l(-1)
    utof r2.y, r2.y
    div r2.x, r2.x, r2.y
    mul r2.y, r1.x, r2.x
    mul r2.y, r0.z, r2.y
    sincos r3.x, r4.x, r1.w
    mul r1.w, r2.y, r3.x
    mul r2.y, r2.y, r4.x
    mul r3.xyz, r1.wwww, cb0[7].xyzx
    mad r2.xzw, r2.xxxx, cb0[6].xxyz, r3.xxyz
    mad r2.xyz, r2.yyyy, cb0[8].xyzx, r2.xzwx
    add r2.xyz, r2.xyzx, cb0[9].xyzx
  else
    mul r0.w, r0.w, r1.x
    iadd r1.x, -r1.z, v0.x
    udiv r0.x, r1.x, r1.x, r0.x
    utof r0.x, r0.x
    mul r0.x, r0.x, r0.w
    iadd r0.w, r1.y, l(-1)
    utof r0.w, r0.w
    div r0.x, r0.x, r0.w
    mul r0.z, r0.z, r0.x
    mul r0.x, r0.x, r0.x
    mad r0.x, cb0[5].w, cb0[5].w, -r0.x
    sqrt r0.x, r0.x
    ishl r0.w, r1.x, l(1)
    utof r0.w, r0.w
    mul r0.w, r0.w, l(3.14159274)
    div r0.y, r0.w, r0.y
    sincos r1.x, r3.x, r0.y
    mul r0.y, r0.z, r1.x
    mul r0.z, r0.z, r3.x
    mul r1.xyz, r0.yyyy, cb0[7].xyzx
    mad r0.xyw, r0.xxxx, cb0[6].xyxz, r1.xyxz
    mad r0.xyz, r0.zzzz, cb0[8].xyzx, r0.xywx
    add r2.xyz, r0.xyzx, cb0[9].xyzx
  endif
else
  mad r2.xyz, v1.xyzx, cb0[4].wwww, cb0[4].xyzx
endif
mul r0.xyzw, r2.yyyy, cb1[1].xyzw
mad r0.xyzw, r2.xxxx, cb1[0].xyzw, r0.xyzw
mad r0.xyzw, r2.zzzz, cb1[2].xyzw, r0.xyzw
add r0.xyzw, r0.xyzw, cb1[3].xyzw
mov r36.xyzw, r0.xyzw
ne r27.x, r0.w, l(1.000000)
if_nz r27.x
  add r26.x, r0.w, -r25.y
  mad r0.x, r25.x, r26.x, r0.x
endif
mov o0.xyzw, r0.xyzw
add r37.x, -r38.y, r36.w
mul r37.y, r38.x, r38.w
mad r37.x, r37.x, r37.y, r36.x
ne r37.y, l(1.000000), r36.w
movc r36.x, r37.y, r37.x, r36.x
mov o1.xyzw, r36.xyzw
ret
// Approximately 0 instruction slots used
